The disclosure relates to a semiconductor device and a method for fabricating the same.
The buried channel array transistor (BCAT) includes gate electrodes buried in trenches, and thus can reduce the impact from short channel effect associated with DRAM structure.
Meanwhile, the ultra large scale integration of DRAM device has continuously reduced the amount, or quantity of charge charged in the capacitor. Accordingly, along with efforts to increase the quantity of charge stored in the capacitor, it is also important to provide leakage current control so as to enhance driving efficiency of the device and the performance thereof.
One of the leakage current in DRAM cell is from leakage current in a gate off state between a gate and a highly-doped storage node, or BC node. Such leakage can be called gate induced drain leakage (GIDL). Accordingly, it is desirable to improve the refresh time (tREF) by controlling such leakage current.